LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY REG IS
    PORT (
        -- indication bit ('1': Start read and close out ;'0': Start out and close read)  
        READ_EN : IN STD_LOGIC;
        -- CLOCK signal
        CLK : IN STD_LOGIC;
        -- read data
        D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        -- out data
        Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END REG;
ARCHITECTURE archREG OF REG IS
    -- Define interconnect signal between Master and Slave
    SIGNAL temp : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    registers : PROCESS (CLK)
    BEGIN
        -- implement Master-Slave Register
        IF (CLK'event AND CLK = '1') THEN
            IF (READ_EN = '1') THEN
                temp <= D;
            ELSE
                Q <= temp;
            END IF;
        END IF;
    END PROCESS;
END archREG; -- archREG